1. Field of the Invention
The present invention relates to: a chip package, a chip carrier, and a method for producing the same; a terminal electrode for a circuit substrate and a method for producing the same; and a complex including the above mentioned chip package mounted on a circuit substrate (hereinafter, such a complex will be referred to as a "chip package-mounted complex").
2. Description of the Related Art
In recent years, the integration degrees of LSIs (Large Scale Integrated Circuits) have remarkably improved, and, accordingly, the number of pins included in one LSI chip has been increasing. As for electronic equipment incorporating LSI chip packages, the size and the thickness thereof have been desired to be reduced. Accordingly, a number of high-density mounting techniques for mounting LSI chips on a circuit substrate at a high density have been developed. A variety of shapes and structures have been proposed for such LSI chip packages (NIKKEI ELECTRONICS 1993. 8.2, No. 587, "LSI package frontier, prompting high-density mounting", pp 93 to 99).
In the present specification, the term "chip carrier" refers to a substrate including terminal electrodes (which are to be connected to electrodes of an LSI chip) and contact electrodes (which are to be connected to a circuit substrate). The term "chip package" refers to a chip carrier with an LSI chip mounted thereon. The chip package, as a whole, is to be mounted on a circuit substrate so as to form a "chip package-mounted complex".
Hereinafter, a method for mounting a conventional chip package onto a circuit substrate will be briefly described.
First, a chip carrier is formed in the following manner. Via holes are formed in a printed circuit board by using a laser beam or by a mold punching technique. A ceramic board may be used instead of a printed circuit board. Terminal electrodes are previously formed on both faces of the printed circuit board. Thereafter, an internal conductor in the printed circuit board is electrically connected to the terminal electrodes by a plating technique or the like. Next, an LSI chip is adhered to an upper face of the above-mentioned chip carrier in a face-up state by using a die bond. Thereafter, electrode pads of the LSI chip are connected to the terminal electrodes present on the upper face of the chip carrier by a wire bonding technique. On the resultant composite, a mold resin is applied so as to cover the LSI chip and the wire bonding, thereby sealing the composite.
Next, a solder layer is formed on the terminal electrodes provided on a lower face (i.e., the face which opposes the circuit substrate when the chip package is mounted on a circuit substrate) of the printed circuit board by printing or the like. Thereafter, the solder is melted by an infrared reflow technique or the like, so as to form solder balls (having diameters in the vicinity of 700 .mu.m). Thus, a chip carrier is obtained. It is also applicable to adhere previously prepared solder balls onto the terminal electrodes of the chip carrier. Thus, a chip package is obtained.
Furthermore, the chip package is positioned with respect to the circuit substrate in such a manner that the solder balls are located in predetermined positions on the circuit substrate. Then, the chip package is disposed on the circuit substrate. Thereafter, the solder balls are melted by an infrared reflow technique or the like, so as to connect the terminal electrodes on the lower face of the chip package to terminal electrodes of the circuit substrate. Thus, a chip package-mounted complex is obtained.
However, the above-mentioned prior art technique has the following problems:
1. Since wire bonding is conducted for connecting the terminal electrodes of the chip carrier to the electrode pads of the LSI chip, an area occupied by the chip carrier becomes larger than an area occupied by the LSI chip. Moreover, because of the mold resin sealing process conducted after the wire bonding connection, the resultant chip package becomes thicker than the height of the loop height of the wire bonding. This hinders the reduction of the size and the thickness of the chip package.
2. Since signals travel through the wire bonding, which have relatively large lengths, the input/output signals are likely to be delayed. Accordingly, the high-frequency characteristics of the chip package deteriorate, so that the chip package is likely to pick up noises.
3. The solder balls, disposed in an array on the lower face of the chip package, prevent the pitch of the terminals of the LSI chip from being reduced. The solder balls are typically arranged at a pitch as large as about 1 mm.
4. The size of the solder balls determines the distance between the chip package and the circuit substrate. In other words, the interval between the chip package and the circuit substrate cannot be made smaller than the size of the solder balls.
5. In the case where the substrate of the chip carrier is made of a different material from that of the circuit substrate, stresses caused by thermal impact will concentrate on the solder connection portions, thereby creating cracks. As a result, the electrical resistance of the solder connection portions may increase.